1. Field of the Invention
The present invention relates generally to a method of manufacturing a stacked-type semiconductor device and, more particularly, relates to technique in which a stacked type structure is formed by bonding a semiconductor substrate having a device formed thereon and another semiconductor substrate together.
2. Description of the Background Art
In order to realize an increased integration density and a larger number of functions of a semiconductor device, attempts have been made to manufacture a stacked-type semiconductor device (so called "three dimensional circuit element") in which circuit elements are stacked up. One example is a method of forming a stacked-type structure by directly bonding two semiconductor substrates each having devices formed thereon, with an insulator interposed therebetween.
FIGS. 17 to 21 show a first example of the background art method for manufacturing a stacked-type semiconductor device. Firstly, referring to FIG. 17, a MOS (Metal Oxide Semiconductor) type field effect transistor having the n conductivity type (hereinafter referred to as "nMOSFET") is formed of a p-type single crystal silicon substrate 1, an insulation oxide film 2, a gate electrode 3 formed of polycrystalline silicon, a conductive interconnection 4 formed of tungsten silicide and source/drain regions 5 doped with n-type impurities. A BPSG (Boro-Phospho Silicate Glass) film 6 including a large amount of boron and phosphorus is deposited on the nMOSFET by CVD and annealed in an atmosphere including oxygen at 900.degree. C. for 30 minutes to planarize BPSG film 6 as shown in FIG. 18.
Then, as shown in FIG. 19, a hole having a cross section 10 .mu.m square is made in BPSG film 6 on conductive interconnection 4, where tungsten 7 is filled. Tungsten 7 is formed by selective CVD. The manufacturing process in a wafer state of pMOSFET (A) is thus completed.
Then, a pMOSFET (B) is formed by the same process as that shown in FIGS. 17 to 19. The pMOSFET (B) includes an insulation oxide film 12 formed on an n-type single crystalline silicon substrate 11, a gate electrode 13, a conductive interconnection 14 and source/drain regions 15 doped with p-type impurities, with tungsten 17 formed in a BPSG film 16 coinciding with tungsten 7 when placed face to face with nMOSFET (A) as shown in FIG. 20.
At last, as shown in FIG. 21, nMOSFET (A) and pMOSFET (B) are put together by pressing, facing each other, and thermally treated in an electric furnace at 900.degree. C. for 20 minutes to be stuck together. In this way, nMOSFET (A) and pMOSFET (B) are completely insulated and isolated from each other. As a result, a C (Complementary) MOSFET is constructed with a stacked-type structure including two layers.
A description will now be made of a second example of the background art method for manufacturing a stacked-type semiconductor device with reference to FIGS. 22 to 26. This background art example of manufacturing processes of a stacked-type semiconductor device was disclosed in Japanese Patent Publication No. 3-16787.
In this background art example, firstly, referring to FIG. 22, a first layer of MOSFET is formed, including an insulation oxide film 22, a gate electrode 23, a conductive interconnection 24 and source/drain regions 25 on a single crystalline silicon substrate 21. Then, an interlayer insulating film 26 is deposited by CVD and the surface thereof is planarized by applying a resist and etching back. An aperture 27 having a cross section 1.3 .mu.m square, extending to single crystalline silicon substrate 21, is made in part of interlayer insulating film 26 in order to form a single crystalline silicon layer on interlayer insulating film 26, which has the same crystal axis as that of single crystalline silicon substrate 21.
Thereafter, as shown in FIG. 23, polycrystalline silicon 28a is filled in aperture 27 by CVD and etching back. Polycrystalline silicon 29 having a thickness of 0.5 .mu.m is formed over interlayer insulating film 26 by CVD. After that, polycrystalline silicon 29 is irradiated with an argon laser beam 30 having a beam diameter of 100 .mu.m moving in a direction indicated by the arrow in the figure at a scanning rate of 25 cm/s. Polycrystalline silicon 29 becomes fused silicon 31 by the irradiation with the argon laser beam 30 and solidified and recrystallized after the irradiation is completed. When fused silicon 31 is solidified, then epitaxial growth is caused in the lateral direction with single crystalline silicon substrate 21 and fused polycrystalline silicon 28a serving as a seed, polycrystalline silicon 28a becomes single crystallized silicon 28, and polycrystalline silicon 29 on interlayer insulating film 26 becomes single crystallized silicon 32 having the same crystal axis as that of single crystalline silicon substrate 21 (see FIG. 24).
Then, referring to FIG. 25, single crystallized silicon 32 is patterned into single crystallized silicon 33 where a MOS transistor is to be formed and single crystallized silicon 34 on aperture 27 by photolithography and etching technique. Thereafter, a MOS transistor in a second layer is formed on single crystallized silicon 33 in the same way as that of the MOS transistor in the first layer (see FIG. 26). The MOS transistor in the second layer includes an insulation oxide film 42, a gate electrode 43, a conductive interconnection 44 and source/drain regions 45.
The background art methods of manufacturing the stacked-type semiconductor devices above had problems as described below.
In the first example of the background art method, it was necessary to apply thermal treatment at 1000.degree. C. or above since nMOSFET (A) and pMOSFET (B) were joined together by sticking BPSG films 6 and 16 together. As a result, there was disadvantageously caused thermal diffusion of the impurities doped in source/drain regions 5 and so on making up the device which had already been formed before the joining process, having an adverse effect on the device characteristics.
There was also the following problem, which was peculiar to formation of the CMOSFET by putting the nMOSFET and the pMOSFET face to face with each other according to the first example of the background art method described above.
P-type single crystalline silicon substrate 1 and n-type single crystalline silicon substrate 11 both must have a certain strength as they serve as substrates for supporting the devices during the manufacturing processes. Accordingly, they must be 500 to 600 .mu.m thick. In the photolithography of the manufacturing processes, a reduction projection alligner, which is mainly used at present, carries out mask alignment using a helium neon laser beam having a wavelength of 6428 .ANG. as a probe beam. Use of the helium neon laser beam as the probe beam enables mask alignment with positional accuracy of 0.3 .mu.m. However, according to the conventional manufacturing method of the stacked-type semiconductor device above, the helium neon laser cannot be used as the probe beam in the process of joining the substrates together since each substrate is at least 500 .mu.m thick and the beam with the wavelength of 6428 .ANG. cannot be transmitted through such a substrate. Accordingly, in the process of joining the substrates together it was necessary to use infrared rays with a wavelength of 2.0 .mu.m capable of being transmitted through a wafer of 500 .mu.m in positioning each single crystalline silicon substrate. As a beam having a long wave length must be used, the positional accuracy in joining the single crystalline silicon substrates together was normally .+-.5 .mu.m, and in the order of .+-.2 .mu.m at best. Therefore, even if the devices on the single crystalline silicon substrates were formed with a design rule of 0.8 to 1 .mu.m, the size of contact for connecting the substrates must be above 10 .mu.m making an allowance for the joining. Accordingly, in forming a CMOS by sticking the substrates together, it was impossible to increase the integration density of the elements up to the present LSI's level.
The second background art method had a problem that, as it included a step of fusing and recrystallizing the polycrystalline silicon layer by the argon laser beam, an intense heat was generated, causing an adverse effect on the characteristics of the devices which had already been formed in the previous processes.
Another possible method of manufacturing a stacked-type semiconductor device like the second background art method described above may be to fix a silicon substrate on the interlayer insulating layer by an adhesive material such as an epoxy resin and form a device on the silicon substrate (for example, see IEDM 85, pp. 684-686). However, interfacial states are generated in the interface between the silicon substrate and the interlayer insulating layer, so that the potential of the silicon substrate is changed, degrading the device characteristics.
It might also be possible to apply technique used in forming an SOI (Silicon on Insulator) MOSFET in which an oxide film and a silicon substrate or two or more silicon substrates are stuck together (see "Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 89-92" and "Proceedings of the 5th Crystal Optics Symposium of Crystal Optics Sectional Committee of the Japan Society of Applied Physics, pp. 31-34"). However, the process of joining the oxide film and the silicon substrate or the two or more silicon substrates also requires thermal treatment in the approximate range of 900.degree. C. to 1100.degree. C., making it impossible to avoid the adverse effect on the device characteristics.